New 
Principal Design Verification Engineer
 Microsoft | |
 United States, Washington, Redmond | |
 Sep 05, 2025 | |
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OverviewMicrosoft Azure is pioneering the fastest network in the public cloud, driving industries into a new era of advanced technology through high-speed cloud computing, artificial intelligence (AI), and machine learning (ML). Within Azure Core, our mission is to build foundational capabilities that empower sectors such as energy, agriculture, healthcare, and personal banking. Azure's innovation has positioned Microsoft as a leader in the public cloud space, unlocking transformative potential through data-driven ecosystems and technological breakthroughs that shape the future for millions worldwide. As a Design Verification Engineer in Azure Core, you will lead a team of engineers in verifying complex hardware designs. You'll define and execute verification plans, develop SystemVerilog testbenches using Universal Verification Methodology (UVM), and collaborate closely with firmware, software, and hardware teams across global sites. Your work will ensure the delivery of high-quality designs for Fully Programmable Gate Arrays (FPGAs) powering millions of cloud servers. This role offers a unique opportunity to strengthen your technical leadership, mentor engineers, and deepen your expertise in UVM. As part of a focused verification team, your contributions will be highly visible and impactful, with room to grow in alignment with your career goals. Microsoft's mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.
Responsibilities* You will write design verification test cases by identifying new tools, test methodologies, and/or best practices that include elements such as success metrics and tracking systems and develop, review and execute test plans for complex or large sized scope feature areas or products and provide guidance to other engineers to execute test plans.* Generate or contribute to a single or multiple project implementation schedules and determine how changes to project schedules and proposed designs impact the hardware engineering aspects of products.* Monitor project progress/status updates across teams and anticipates potential challenges, sharing details with key stakeholders as necessary (e.g., proactively resolve design issues, advise on resource requirements, and/or identify feasible alternatives).* Advise others regarding the appropriate test requirements and improvements to be included in relevant, highly complex hardware designs and specifications and review documentation to help ensure that the appropriate test requirements and improvements are included in relevant hardware designs and specifications by applying an understanding of how complex features or products work under a variety of scenarios.* Develop System Verilog based testbenches using Universal Verification Methodology (UVM) testbenches for use within block level and subsystem level test environments along with reusable, configurable verification components for use across verification teams and to be leveraged for future design verification applications and projects. | |