Principal Engineer, Analog/Mixed Signal Design (SoC/CMOS)

This is a direct salaried position with our client that specializes in low power consumption IoT wireless module products. The salary range is $190K - $220K+ DOE. The employee can work out of their San Jose or San Diego offices. Full time onsite or hybrid coming in weekly a possible option.

In this role, you will be partnering with a team of cross functional engineers to develop novel SoC products for connectivity and communications. This position has high visibility and impact on the success of the project and may also oversee a team of RFIC design engineers.

This position can be based in San Diego or San Jose. It can be onsite full time or a hybrid work environment coming into the office multiple days a week, providing an excellent balanced environment for a results-oriented individual committed to continuous improvement, learning, and collaboration.

Key Responsibilities:

• Technical leadership in developing integrated custom analog, and mixed signal IPs.
• Hands on contribution on all aspects of the design of high-performance integrated sigma-delta and SAR analog-to-digital converters (ADCs) in advanced CMOS processes.
• Supervising layout activities and performing post-layout LPE simulations and analysis.
• Working closely with RF, analog, digital, test, and firmware design engineers.
• Presenting to peers and management.
• Working with the System Engineers to derive block level specifications based on target product requirements.
• Run behavioral model simulations to study system performance and drive block-level specifications (Matlab, VerilogA).
• Partnering with the System and Digital Engineers to design and validate methods and algorithms to alleviate circuit impairments by calibration, compensation, pre-distortion, and various other techniques.
• Assisting Test Engineers on the design of comprehensive test plan, including defining, developing, and ramping up production ATE solutions.
• Participating in post-silicon bring-up, detailed performance characterization, optimization, and debug including the use of lab instruments.

• Excellent technical knowledge of CMOS fundamentals and transistor level design and implementation of high-sampling-rate high-resolution sigma-delta and SAR ADCs.
• Hands on experience in transistor-level design of high-performance data-converter related circuits, such as: voltage and current references, OpAmps, comparators, integrators, sample-&-hold, current and capacitive DACs, oscillators, filters, etc.
• Experienced in optimization for power consumption, SNR, PN/jitter, matching, conversion time, area, etc.
• Good familiarity with IC layout, full IC design flow and verification.
• Strong intuitive, analytical, and problem-solving skills, strong initiative, attention-to-detail, highly organized, and personal commitment to quality.
• Familiar with using various development tools: Cadence Virtuoso suite, Calibre, PVS, Matlab, MS Office, etc
• Team player with a strong sense of urgency to meet product timeline.
• Ability to work well on multiple tasks simultaneously.
• Ability to work well on multi-site teams.
• Excellent written and verbal communication and presentation skills, including the ability to articulate and explain circuit and system design decisions for both internal design documents and external reports or proposals.
• Direct experience in IoT, WiFi and Bluetooth products, circuits, and systems